Integrated circuit devices (hereinafter referred to as chips) having high performance are typically electronically packaged by mounting one or more chips onto a ceramic, e.g., alumina, circuitized substrate (referred to as a chip carrier) and using wire bonds to electrically connect I/O (input/output) contact pads on each chip to corresponding contact pads (and therefore to corresponding fan-out circuitry) on the circuitized chip carrier substrate. Wire bonding is a well known process in the art and further description is not believed necessary. The resulting chip carrier is then typically mounted on a printed circuit board (PCB) and, using circuitry on the PCB, electrically coupled to other such chip carriers and/or other electronic components mounted on the PCB.
While ceramic chip carrier structures have proven extremely useful in the electronic packaging field, the use of ceramic as the dielectric material of the substrate does present certain limitations and drawbacks. For example, the speed of propagation of an electrical signal through a conductive wire located on a dielectric layer (or between two dielectric layers for that matter) is proportional to the inverse of the square root of the dielectric constant of the dielectric material layer or layers. As is known, the dielectric constants of most ceramics are relatively large, e.g., the dielectric constant of alumina (the primary constituent of ceramic materials used in these substrates) is relatively high, which results in ceramic chip carriers exhibiting relatively low signal propagation speeds in comparison to substrates of other (e.g., organic) materials, such as fiberglass-reinforced epoxy resin, polytetrafluoroethylene, etc.
Utilization of ceramic chip carrier substrates also presents certain I/O constraints. For example, a single-layer ceramic chip carrier substrate includes but a single layer of fan-out circuitry on the upper surface of the ceramic substrate, extending to contact pads around the outer periphery of the substrate. A lead frame having inner leads connected to these peripheral contact pads, is typically used to electrically connect such a ceramic chip carrier to a PCB. As the number of chip I/Os has increased (in response to more recent enhanced design requirements), it has been necessary to increase the wiring density, sometimes to the point where undesirable cross-talk between adjacent wires may occur. Further, it has become increasingly difficult, if not impossible, to form a correspondingly large number of contact pads around the outer periphery of the ceramic substrate. Accordingly, it is understood that single-layer ceramic chip carrier substrates are limited in the ability thereof to accommodate semiconductor chips with significantly increased I/O counts as demanded in many of today's designs.
Various efforts to accommodate chips having relatively large numbers of I/O pads have led to the use of multilayer ceramic chip carrier substrates utilizing what are referred to as "ball grid arrays" (BGAs) in lieu of lead frames. Such multilayer types of ceramic chip carrier substrates differ from single-layer ceramic chip carrier substrates in that these include two or more layers of fan-out circuitry on two or more ceramic layers. Significantly, these layers of fan-out circuitry are electrically interconnected by mechanically drilled holes (called "vias"), which are plated and/or filled with electrically conductive material (e.g., copper). In addition, a certain number of such holes extend from the layers of fan-out circuitry to respective lands on the chip carrier substrates, on which are mounted solder balls (formed in grid arrays, hence the term "ball grid array"). These solder balls are intended to be mechanically and electrically connected to corresponding solderable contact pads on a receiving substrate, e.g., PCB. Unfortunately, the mechanically drilled holes electrically interconnecting the layers of fan-out circuitry have relatively large diameters, requiring the spacing between the fan-out wires to be relatively large. This relatively large spacing between fan-out wires understandably limits the number of chip I/O pads which can be accommodated by such multilayered substrates.
Other attempts to package chips having a relatively large number of chip I/O pads have led to the use of multi-tiered cavities in multi-layered ceramic substrates. (As used herein, the term "cavity" denotes a depression in a substrate, not a hole or opening extending entirely through the substrate's thickness.) When using such a packaging configuration, a chip is mounted face-up (its I/O pads facing upwardly) at the bottom of a multi-tiered cavity. Wire bonds (e.g., using fine gold wire) are extended from the I/O contact pads on the exposed upper surface of the chip to respective contact pads on the exposed upper surfaces of the different layers of the multi-layered ceramic substrate. While this configuration does make it possible to accommodate a relatively large number of chip I/O pads, it unfortunately typically mandates usage of multiple manufacturing set-up operations to accommodate the different tier height for the relatively long wire bonds extending from the chip to the tiers of the multi-tiered cavity.
Ceramic chip carrier substrates are also limited in heat dissipation capabilities. For example, in the case of a multilayer ceramic chip carrier having a chip positioned at the bottom of a multi-tiered cavity, heat dissipation is typically achieved by providing a heat sink directly beneath the cavity. This implies, however, that the heat generated by the chip must necessarily be conducted through the ceramic layer at the bottom of the cavity before reaching the heat sink. As a consequence, the rate of heat dissipation is limited.
As defined herein, the present invention teaches a method for making a circuitized substrate capable of overcoming the aforementioned drawbacks of other such products. This method is uniquely adaptable for use with many existing manufacturing apparatus (e.g., wire bond and photoimaging equipment) without extensive alteration thereof and can thus be used on a mass production basis to enjoy the benefits thereof.
Various methods for making circuitized substrates are described in U.S. Pat. No. 5,022,960 (Takeyama et al), U.S. Pat. No. 5,142,448 (Kober et al), U.S. Pat. No. 5,144,534 (Kober) and U.S. Pat. No. 5,288,542 (Cibulsky et al). In U.S. Pat. No. 5,022,960, a laser beam is used to remove a selected portion of a substrate (12) which eventually accommodates a semiconductor chip (20) positioned on a metal layer (11) also attached to the substrate. In U.S. Pat. No. 5,142,448, there is described the step of compression molding several dielectric layers to form a laminate. Flexibility of certain parts of the board is attained by provision of slots, and a "plug" is located for occupying the defined flexible region. In U.S. Pat. No. 5,144,534, a method of making rigid-flexible circuit boards is described in which a removable plug is used in the PCB during processing and then removed. Finally, in U.S. Pat. No. 5,288,542 (assigned to the same assignees as the present Application), another method is described for making a rigid-flexible circuit board in which a release layer (6) is used during processing and subsequently removed.
In addition to the above, attention is directed to the following patents assigned to the same assignee as the present invention.
In U.S. Pat. No. 5,542,175, entitled "Method Of Laminating And Circuitizing Substrates Having Openings Therein", filed Dec. 20, 1994, there is defined a method of laminating two substrates and circuitizing at least one of these. A plug is provided and shaped to fit within an opening defined in the structure, and then removed following lamination and circuitization.
In U.S. Pat. No. 5,798,909, entitled "Organic Chip Carriers For Wire Bond-Type Chips", filed Feb. 15, 1995, there is defined a chip carrier having a single-tiered cavity within a dual layered (of organic material) substrate and a semiconductor chip located in the cavity. The chip is wire bonded to circuitry on the substrate. The method claimed in the present Application may be used to make a chip carrier of the type defined in U.S. Pat. No. 5,798,909.
In U.S. Pat. No. 5,566,448, entitled "Method Of Construction Of Multi-Tiered Cavities Used In Laminate Carriers", filed Jun. 26, 1995, there is defined a method of forming a chip module wherein a rigid cap and substrate are used, the cap and substrate laminated together with bond pads connected to circuitry disposed in a bottomed cavity of the cap. Following cap circuitization, part of the cap (that over the cavity) is removed and a semiconductor chip coupled to the circuitry.
In U.S. Pat. No. 5,599,747, entitled "Method Of Making A Circuitized Substrate With An Aperture", filed Jun. 27, 1995, there is defined a method of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization then occur, following which the temporary support portion is removed. This temporary support thus assures effective support for the photoresist used a part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc., which may adversely impact subsequent processing steps.
The teachings of U.S. Pat. Nos. 5,542,175, 5,798,909, 5,566,448 and 5,599,747 are hereby incorporated herein by reference.
As defined herein, the present invention defines a method that results in a circuitized substrate capable of: (1) exhibiting relatively high electrical signal propagation speeds; (2) accommodating relatively high I/O chips; (3) exhibiting relatively short "time of flight" electrical signal speeds; and (4) exhibiting a relatively high rate of heat dissipation.